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EISA Bus Technical Summary

Table of Contents

1.0 EISA Overview

2.0 EISA Documents

3.0 EISA Signal Descriptions

4.0 EISA Connector Pinout

1.0 EISA Overview

The EISA Bus originated in 1988 & 1989. It was developed by the so called "Gang of Nine" (AST, Compaq, Epson, Hewlett-Packard, NEC, Olivetti, Tandy, Wyse and Zenith) as an alternative to IBM's "patented" Micro Channel bus. It received limited use in 386 and 486 based Personal Computers through about 1995 before being obsoleted by the PCI bus as Pentium based systems were introduced.

EISA incorporates many of the benefits of the Micro Channel bus while maintaining compatibility with legacy ISA expansion boards. EISA connectors are a superset of the 16-bit connectors used on ISA system boards. ISA 8-bit and 16-bit expansion boards can be installed into the ISA compatible portion of the EISA slot. EISA expansion boards use the signals on the ISA compatible portion of the connector as well as additional signals that provide enhanced function and performance.

EISA introduced the following enhancements over ISA:

2.0 EISA Documents

2.1 EISA Specification

The Extended Industry Standard Architecture, or "EISA", bus is defined in the EISA Specification, Version 3.12. At last check, this document could be ordered for a fee from Global Engineering Services.

2.2 EISA Books

Two books that provide good descriptions of the EISA bus are:

3.0 EISA Signal Descriptions

3.1 Address and Data Bus Signal Group

This section describes the bus signals used for memory and I/O addressing and bus signals used for transfer of data.
BE*<3:0> - (EISA Connector)
BE*<3:0> are the byte enable siganals that identify the specific bytes addressed in a dword. BE*<3:0> are pipelined from one cycle to the next and must be latched by the address slave if required for the whole cycle. The timing of these signals varies depending on the signal type. During normal cycles, they go valid before BALE goes active and remain valid as long as the LA<31:2> lines remain valid. During DMA or 16-bit ISA bus master cycles, they go valid at least 1/2 BCLK before the CMD* or ISA command signals go active. It is permissible for a 32-bit bus master to drive both the high bytes of the data bus on write cycles even if it only places valid data (as indicated by BE*<3:0> lines) on one of the high bytes.
D<31:24> - (EISA Connector)
D<31:24> are the highest order 8 bits of the 32-bit EISA data bus. A 32-bit device uses D<31:24> to transfer the fourth (highest) byte of dword when the address line BE*<3> is asserted.
D<23:16> - (EISA Connector)
D<23:16> are the second highest order 8 bits of the 32-bit EISA data bus. A 32-bit device uses D<23:16> to transfer the third (second highest) byte of dword when the address line BE*<2> is asserted.
D<15:8> - (ISA Connector)
D<15:8> are the high 8 bits of the 16-bit data bus. Sixteen bit devices use these lines to transfer the high half of a data word when SBHE*, BE*<3>, or BE*<1> is asserted, thirty-two bit devices use D<15:8> to transfer the second (third highest) byte of a dword when the address BE*<1> is asserted.
D<7:0> - (ISA Connector)
D<7:0> are the low 8 bits of the data bus. Eight bit devices use these lines to transfer data. A sixteen bit device uses these lines to transfer the low half of a data word when the address line SA<0> is low or when BE*<2> or BE*<0> is asserted. Thirty-two bit devices use D<7:0> to transfer the first (lowest) byte of a dword when the address BE*<0> is asserted.
LA<16:2> - (EISA Connector)
LA<16:2> are a part of the lachable address bus. The latchable address lines (LA<31:2>) are pipelined from one cycle to the next and must be latched by the addressed slave if required for the whole cycle. LA<31:2> are presented early enough in the cycle decode to support 1.5 or 2 BCLK memory accesses. During standard cycles, they go valid before START* is asserted and remain valid at least 1/2 BCLK after CMD* or the ISA command signals are asserted. During DMA or 16-bit ISA bus master cycles, LA<31:2> are valid at least one BCLK before the CMD* or ISA command signals are asserted. LA<31:2> can be driven by an expansion board acting as a bus master. An EISA slave may latch the entire address (LA<31:2> and BE*<3:0>) and status signals (M-IO and W-R) on the trailing edge of START* or leading edge of CMD*.
LA<23:17> - (ISA Connector)
LA<23:17> are part of the 32-bit latchable address bus. They have the same characteristics as LA<16:2>, except that they are wired to the 16-bit portion of the ISA connector. An ISA slave can latch LA<23:17> with the trailing edge of BALE.
LA*<31:24> - (EISA Connector)
LA*<31:24> are the highest byte of the 32-bit latchable address bus. They have the same characteristics as the LA<16:2>, except that they use inverted logic. A high on a LA*<31:24> address bit must be interpreted as an address bit of "0". A low must be interpreted as an address bit of "1". (When the notation LA*<31:2> is used, only LA<31:24> are active low, the next are active high.)
SA<19:0> - (ISA Connector)
The SA<19:0> lines address memory or I/O devices within the system. They form the low-order 20 bits of the 32-bit address. On normal cycles SA<19:0> are driven onto the bus while BALE is high and are latched by the system board on the trailing edge of BALE. SA<19:0> are valid throughout the bus command cycle. On DMA or 16-bit ISA bus master cycles SA<19:0> are valid nominally one BCLK before the command signals and remain valid nominally one BCLK after the command signals go away.
SBHE* - (ISA Connector)
SBHE* (System Byte High Enable) indicates (when low) that expansion boards that support 16-bit data transfers should drive data on the high half of the D<15:0> data bus. On normal cycles, SBHE* becomes valid on the bus when BALE is asserted and remains valid until after the command (MRDC*, MWTC*, IORC*, IOWC*, or CMD*) is negated. On DMA or 16-bit ISA bus master cycles, SBHE* is valid nominally one BCLK before the command signals and remains valid nominally one BCLK after the command signals go away.
AENx - (ISA Connector)
This slot specific (the "x" refers to the slot number) signal, when negated (low), indicates that an I/O slave may respond to addresses and I/O commands on the bus. AENx is asserted (high) during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. The system board must negate AENx when START* is asserted for an I/O access, and AENx must remain negated until after CMD* is asserted. AENx is also used to disable I/O accesses to all other option slots during accesses to a particular slot's slot specific I/O address range.

3.2 Data Transfer Control Signal Group

This section describes the signals used to control data transfer cycles on the 8-, 16-, and 32-bit bus.
BCLK - (ISA Connector)
BCLK is provided to synchronize events with the main system clock. BCLK operates at a frequency between 8.333 MHz and 4 MHz, with a normal duty cycle of 50 percent. BCLK is driven only by the system board. The BCLK period is sometimes extended for synchronization to the main CPU or other system board devices. For example, the COMPRESSED cycle type extends each BCLK period by holding BCLK low for half a cycle beyond the normal transition to high. The BCLK extension facilitates synchronization during the 1.5 BCLK COMPRESSED cycle. During bus master accesses the system board extends BCLK only when required to synchronize with main memory. Events must be synchronized to BCLK edges without regard to frequency or duty cycle. BCLK is always synchronous with the trailing edge of START* and the leading edge of CMD*. BCLK may not be synchronous with the leading edge of START* or the trailing edge of CMD*.
MSBURST* - (EISA Connector)
Bus master asserts MSBURST* to indicate to the burstable slave that the bus master will execute burst cycles. MSBURST* may only be asserted after SLBURST* is sampled asserted and when no cycle translation is required. A bus master asserts MSBURST* with the LA<31:2> address lines for the second and all subsequent cycles of the burst and the slave samples MSBURST* on the BCLK rising edge.
SLBURST* - (EISA Connector)
A slave (typically, main memory) indicates its support of Burst cycles by asserting SLBURST*. The slave develops SLBURST* from the LA<31:10> address lines and M-IO and produces SLBURST* regardless of the state of MSBURST*. A memory slave that asserts SLBURST* must sample memory write data on or before a rising BCLK edge with CMD* asserted (regardless of the state of MSBURST*). SLBURST* is sampled on the rising edge of BCLK by the main CPU, DMA controller or bus master.
M-IO - (EISA Connector)
The main CPU or an EISA bus master asserts M-IO to indicate the type cycle in progress as a memory cycle (high) or I/O cycle (low). M-IO is pipelined from one cycle to the next and is latched by the addressed slave if needed for the whole cycle. M-IO should be included in all decodes by EISA slaves. M-IO must not be used in decoding the signals M16* or IO16*.
LOCK* - (EISA Connector)
The main CPU or a bus master may assert LOCK* to guarantee exclusive memory access during the time LOCK* is asserted. A bus master may also assert LOCK* to guarantee exclusive I/O access during the time LOCK* is asserted. Assertion of LOCK* allows test-and-set operations (as used for semaphores) to be executed as a unit, with the bus lock preventing multiple devices from simultaneously modifying the semaphore.
EX32* - (EISA Connector)
A memory or I/O slave asserts EX32* to indicate that it supports 32-bit (dword) transfers. A two BCLK cycle is executed when a slave asserts EX32* during a memory access. The slave asserts EX32* after decoding a valid address on the LA<31:2> address lines and M-IO. EX32* should not be latched by the slave. Both 16- and 32-bit EISA bus masters must monitor EX32* at the trailing edge of START* to determine if the slave supports 32- (and 16-) bit EISA transfers (asserted), or if the system board is performing data size translation (negated). If data size translation is being done and the master is a 32-bit master, then the system board asserts EX32* to indicate completion of the translation.
EX16* - (EISA Connector)
An EISA memory or I/O slave asserts EX16* to indicate that it supports 16-bit (word) transfers. A 16-bit EISA bus master samples EX16* asserted to confirm a 16-bit EISA slave. An EISA cycle (two BCLK) is executed when a slave asserts EX16* during a memory access by the system board or a 16-bit EISA bus master. The slave asserts EX16* after decoding a valid address on the LA<31:2> address lines and M-IO. EX16* should not be latched by the slave. 16-bit EISA bus masters must monitor EX16* to determine if the slave supports 16-bit EISA transfers (asserted), or if the system board is performing data size translation (negated). If data size translation is being done (ISA cycles) and the master is a 16-bit master (indicated by the master asserting MASTER16*), then the system board asserts EX16* to indicate completion of the translation.
EXRDY - (EISA Connector)
EISA I/O and memory slave negate EXRDY to request wait state timing (each wait state is one BCLK). The system board samples EXRDY on each falling edge of BCLK after it asserts CMD*. (On cycles to ISA slaves EXRDY is sampled on each falling edge of BCLK after IORC*, IOWC*, MDRD*, and MWTC* are asserted.) The system board holds CMD* asserted during the entire period EXRDY is negated, and at least one half BCLK after sampling EXRDY asserted. EXRDY must be driven with an open-collector type buffer (a system board pullup resistor provides the asserting drive current). The EISA slave should negate EXRDY during START* or on the rising edge of BCLK at the end of START* if wait states are to be added. The slave must allow EXRDY to float high (asserted) synchronously with BCLK falling edge and must not hold EXRDY negated longer than 2.5 µs. EXRDY should never be driven high.
START* - (EISA Connector)
The START* signal provides timing control at the start of a cycle. The CPU or bus master asserts START* after LA<31:2> and M-IO become valid and negates START* on a rising edge of BCLK after one BCLK cycle time. BE*<3:0> and W-R may not be valid at the leading edge of START*.
CMD* - (EISA Connector)
CMD* provides timing control within the cycle. The system board asserts CMD* on the rising edge of BCLK, simultaneously with negation of START*. The system board hold CMD* asserted until the end of the cycle. The end of the cycle normally is synchronized with the rising edge of BCLK, but in certain cases is asynchronous. A bus master does not drive CMD*.
W-R - (EISA Connector)
The status signal, W-R, identifies the cycle as a write (high) or read (low). W-R becomes valid after assertion of START* and before assertion of CMD*. W-R remains valid as long as address lines LA<31:2> are valid. W-R is driven from the same edge of BCLK that activates the START* signal.
BALE - (ISA Connector)
BALE (when high) indicates that a valid address is present on the LA<31:2> address lines. The LA<31:2> address lines or any decodes developed from them by ISA devices are latched (with transparent latches) on the trailing edge of BALE if the address is needed for the whole cycle. BALE is always high during a DMA or 16-bit ISA bus master operation. EISA devices should not use BALE to latch addresses; the trailing edge of START* or leading edge of CMD* should be used.
MRDC* - (ISA Connector)
The system board or ISA bus master asserts MRDC* to indicate that the addressed ISA memory slave should drive its data onto the memory bus. MRDC* is asserted for read accesses to memory, except when inhibited by assertion of EX32* or EX16* (an EISA device responded). During ISA Compatible DMA cycles, MRDC* is asserted for read accesses to memory addresses between 00000000h to 00FFFFFFh, regardless of the type of memory responding. A DMA device should not use MRDC* to decode its I/O address. MRDC* is also asserted for refresh cycles. MRDC* can be driven by an expansion board acting as an ISA 16-bit bus master.
MWTC* - (ISA Connector)
The system board or ISA bus master asserts MWTC* to indicate that the addressed ISA memory slave may latch data from the memory bus. MWTC* is asserted for write accesses to memory, except when inhibited by assertion of EX32* or EX16* (an EISA device responded). During Compatible DMA cycles, MWTC* is asserted for write accesses to memory addresses between 00000000h and 00FFFFFFh, regardless of the type of memory responding. A DMA device should not use MWTC* to decode its I/O address. MWTC* can be driven by an expansion board acting as an ISA 16-bit bus master.
SMWTC* - (ISA Connector)
The system board asserts SMWTC* to indicate that the addressed memory slave may latch data from the memory bus. SMWTC* is only asserted for ISA write accesses to memory addresses between 00000000h to 000FFFFFh. SWMTC* is derived from MWTC* and has similar timing.
SMRDC* - (ISA Connector)
The system board asserts SMRDC* to indicate that the addressed memory slave should drive its data onto the memory bus. SMRDC* is only asserted for ISA read accesses to memory addresses between 00000000h to 000FFFFFh or refresh cycles. SMRDC* is derived from MRDC* and has similar timing.
IOWC* - (ISA Connector)
The system board or ISA bus master asserts IOWC* to indicate that the addressed ISA I/O slave may latch data from the EISA bus. IOWC* is asserted for I/O write accesses, except when inhibited by assertion of EX32* or EX16* (an EISA device responded). An ISA I/O slave latches data from the data bus when IOWC* is asserted and AENx is negated. The main CPU or bus master must drive valid data on the bus before asserting IOWC*. A DMA device can latch data from the data bus when IOWC* is asserted.
IORC* - (ISA Connector)
The system board or ISA bus master asserts IORC* to indicate that the addressed ISA I/O slave should drive its data onto the EISA bus. IORC* is asserted for I/O read accesses, except when inhibited by assertion of EX32* or EX16* (an EISA device responded). An ISA I/O slave drives data onto the bus while IORC* is asserted and AENx is negated (low). The device must hold the data valid until sampling IORC* negated. A DMA device can drive data on the data bus after sampling IORC* asserted.
CHRDY - (ISA Connector)
An ISA memory or I/O slave can negate CHRDY to lengthen a bus cycle from the default time. The slave negates CHRDY after decoding a valid address and sampling the command signal (MRDC*, MWTC*, SMRDC*, SMWTC*, IORC*, or IOWC*) asserted. When the slave's access has completed, CHRDY should be allowed to float high (asserted). Bus cycles are lengthened by an integral number of BCLK cycles. The ISA command signals remain active at least one BCLK after the slave asserts CHRDY. CHRDY should be driven with an open collector type driver, and should never be driven high. CHRDY may not be held low for more than 2.5 µs. EISA slaves should never negate CHRDY.
NOWS* - (ISA Connector)
An ISA memory slave asserts NOWS* (No Wait State) after its address and a command have been decoded to indicate that the remaining clock cycles are not required. NOWS* must be asserted before the falling edge of BCLK to be recognized during ISA cycles. During EISA cycles, an addressed EISA slave may assert NOWS* before the main CPU negates START* to generate COMPRESSED cycles (1.5 BCLKs/cycle). A slave should not assert NOWS* and negate EXRDY or CHRDY during the same cycle.
M16* - (ISA Connector)
M16* signals the system that the addressed ISA memory is capable of transferring 16 bits of data at once. When M16* is asserted, during a memory read or write and is not superseded by EX32* or EX16*, the ISA compatible three BCLK memory cycle is run. M16* is decoded from LA<23:17>. M-IO is not included in the decode and M16* should not be latched by the ISA slave. Only ISA memory slaves need to generate M16*; the system board generates M16* from EX32* or EX16* for EISA memory slaves. M16* should only be driven with an open collector type of driver.
IO16* - (ISA Connector)
A 16-bit ISA I/O slave asserts IO16* (after decoding a valid address on SA<15:1>) to indicate its 16-bit data size. The system board defaults to a three BCLK I/O cycle when it samples IO16* asserted by an ISA I/O slave (EX32* and EX16* negated). IO16* should only be driven with an open collector type of driver.

The system board does not automatically assert IO16* when a 16-bit ISA bus master accesses an EISA I/O slave. EISA slaves that support 16-bit ISA bus masters must assert IO16* as well as EX32* (or EX16*) when addressed. The 16- or 32-bit EISA I/O slave should decode the LA<11:2> address with AENx low (do not include M-IO), and latch the result in a transparent latch which is open when BALE is high. The output from the latch is used to control the assertion of IO16*. EISA I/O slaves that do not support 16-bit ISA bus masters need not assert IO16*.

3.3 Bus Arbitration Signal Group

This section describes signals used to arbitrate for bus control. These signals are a combination of new EISA signals and existing ISA signals.
MREQx* - (EISA Connector)
MREQx* is a slot specific signal used by EISA bus masters to request bus access. The "x" refers to the slot number. Bus masters requiring use of the bus must assert MREQx* until the system board grants bus access by asserting MAKx*. The requesting device must hold MREQx* asserted until the system board asserts the appropriate MAKx* signal. The system board samples MREQx* on the rising edge of BCLK. If MREQx* is sampled asserted, the arbitration controller performs the arbitration and the system board asserts MAKx* when the bus becomes available. The bus master can begin driving the bus with address and other signals on the falling edge of BCLK when MAKx* is sampled asserted.

When a bus master completes a transfer, it can release the bus by negating MREQx* on the falling edge of BCLK. If no bus cycle is in progress when MREQx* is negated, the bus master must float LA<31:2>, BE*<3:0>, MSBURST*, LOCK*, D<31:0>, START*, M-IO, and W-R on or before the rising edge of BCLK after MREQx* is negated. If a cycle is in progress when MREQx* is negated, then the LA<31:2>, BE*<3:0>, MSBURST*, LOCK*, START*, M-IO, and W-R signals must be floated by the rising edge of BCLK at the end of the cycle. The data signals D<31:0> must be floated on (EXRDY termination) or before (EX32* or EX16* termination) the falling edge of BCLK after the end of the cycle. Cycle completion is indicated by the memory or I/O slave asserting EXRDY or the system board asserting EX16* or EX32* after completing bus conversions. A bus master must wait at least two BCLKs after releasing the bus before re-asserting its MREQx*. The trailing edge of MREQx* must meet the setup and hold time to the sampling point for proper system operation.

An EISA bus may provide EISA slots that do not support an EISA bus master. The non-bus master EISA slot must hold MAKx* permanently negated and must not connect any signal to the MREQx* connector pin.

MAKx* - (EISA Connector)
MAKx* is a slot specific signal that is asserted by the system board to grant bus access to an EISA bus master. The "x" refers to the slot number. MAKx* is asserted from the rising edge of BCLK and the bus master can begin driving LA<31:2>, BE*<3:0>, MSBURST*, START*, M-IO, and W-R on the next falling edge of BCLK. The system board negates MAKx* on the rising edge of BCLK after sampling MREQx* negated. The system board can also negate MAKx* to indicate to an active bus master that another device has requested the bus. The bus master must negate MREQx* to release the bus within 64 BCLKs (8 µs) of sampling MAKx* negated.

EISA system slots do not have to be capable of supporing an EISA bus master adapter. However, EISA slots that do not support EISA bus master adapters should have MAKx permanently in the inactive state (+5 volts) and should not have MREQx* connected.

DRQ<7:5>, DRQ<3:0> - (ISA Connector)
The DRQ<x> lines are used to request a DMA service from the DMA subsystem or for a 16-bit ISA bus master to request access to the system bus. The request is made when DRQ<x> is asserted. The system board allows DRQ<x> to be asserted asynchronously. The requesting device must hold DRQ<x> asserted until the system board asserts the appropriate DAK*<x> signal. For demand mode DMA memory-read I/O-write cycles, DRQ<x> is sampled on the rising edge of BCLK, one BCLK from the end of the cycle (the rising edge of IOWC*). For demand mode DMA memory-write I/O-read cycles, DRQ<x> is sampled on the rising edge of BCLK, 1.5 BCLKs from the end of the cycle (the rising edge of IORC*). For demand mode Burst DMA, DRC<x> is sampled each cycle on the rising edge of BCLK. For 16-bit ISA bus masters, DRQ<x> is sampled on the rising edge of BCLK, two BCLKs before the system board negates DAK*<x>. The trailing edge of DRQ<x> must meet the setup and hold time to the sampling point for proper system operation.
DAK*<7:5>,DAK*<3:0> - (ISA Connector)
The system board asserts a DMA channel's DAK*<x> to indicate that the channel has been granted the bus. A DMA device is selected if it decodes DAK*<x> with IORC* or IOWC* asserted. DAK*<x> can also be used to acknowledge grant of bus access to a 16-bit ISA bus master. The bus master must assert MASTER16* after sampling DAK*<x> asserted. Address and cycle control signals must be floated and MASTER16* must be negated before the system board negates DAK*<x>. For EISA block or demand mode DMA transfers, DAK*<x> remains asserted until the transfer completes or until the centralized arbitration controller preempts the DMA process. The preemption occurs after another device requests the bus and 4 µs elapses.
T-C - (ISA Connector)
This signal is bidirectional, acting in one of two modes, depending on the programming of the channel. In the output mode, the system board asserts T-C to indicate that a DMA channel's word count has reached terminal count. Terminal count is indicated when the decrementing word count "rolls over" from zero to FFFFFFh. The system board asserts T-C only while asserting the channel's DAK*<x>. A DMA device decodes T-C with the appropriate DAK*<x> asserted to determine when the transfer has completed.

In the input mode, T-C can be used by a DMA slave to stop a DMA transfer. During ISA Compatible, Type "A", or Type "B", transfers, T-C is sampled by the system while IORC* or IOWC* is asserted. During Burst cycles, T-C is sampled at the same time as the DRQ<x> input, on the rising edge of BCLK. If it is sampled asserted the transfer is terminated, and if auto-initialize is programmed, the transfer restarts at the beginning.

MASTER16* - (ISA Connector)
A bus master asserts MASTER16* to indicate 16-bit data size. A bus master can assert MASTER16* after the system board asserts DAK*<x> or MAKx*. The 16-bit EISA bus master negates MASTER16* after completing the last transfer. An ISA master negates MASTER16*, immediately when the system board negates DAK*<x>. A 32-bit bus master can assert MASTER16*, immediately when the system board negates DAK*<x>. A 32-bit bus master can assert MASTER16* during START* to disable automatic 32-to-16-bit data size translation for 16-bit EISA memory Burst slaves. It can then perform 16-bit Burst cycles to a 16-bit EISA slave.
REFRESH* - (ISA Connector)
REFRESH* is used to indicate (when low) a refresh cycle in progress. REFRESH* causes SA<15:0> (or LA<15:2>) to drive the row address inputs of all DRAM banks so that when MRDC* (or CMD*) is asserted, the entire system memory is refreshed at one time.

3.4 Utility Signal Group

This section describes a variety of general utility signals. These signals are all on the ISA connector.
OSC - (ISA Connector)
OSC is a clock for use in timing applications. Its frequency is 14.31818 MHz with a 50 percent duty cycle.
RESDRV - (ISA Connector)
Assertion of RESDRV causes a hardware reset of ISA and EISA expansion boards. RESDRV is asserted by the reset controller during power up or after a bus timeout. Software can cause assertion of RESDRV by setting I/O port 0461h bit 0 to a "1". RESDRV is negated when the software resets this bit to a zero. RESDRV has a minimum pulse width equivalent to 9 BCLK periods. All devices that can prevent operation of the CPU, memory or system board I/O must use RESDRV for hardware reset. When RESDRV is asserted, these devices must float all 3-state outputs which drive the EISA bus. These outputs are not permitted to drive the EISA bus after RESDRV has been asserted until the device is initialized. Slaves that insert wait states based on internal state machines, devices that require software initialization, and DMA devices are examples of hardware that reset after sampling RESDRV asserted.
IRQ<15:14>, IRQ<12:9>, IRQ<7:3> - (ISA Connector)
The IRQx lines are used to interrupt the CPU to request some service. In compatible mode, the interrupt is recognized when IRQx goes from a low to a high and remains there until the appropriate interrupt service routine is executed. If programmed to level-sensitve mode, the interrupt is recognized when the IRQx signals is asserted (low). Another interrupt is generated at the end of the interrupt service routine if the IRQx signal is still held low, allowing a single line to be shared by more than one device. IRQ<15:3> are pulled up by the system board. A floated interrupt line is guaranteed to stabilize at a TTL "high" after 500 ns. Interrupt service routines must reset the interrupt latch (which floats the interrupt line), then wait at least 500 ns before issuing the end-of-interrupt command and enabling interrupts.
IOCHK* - (ISA Connector)
An EISA or ISA expansion board can assert IOCHK* to signal the main CPU that a serious error has occurred. Assertion of IOCHK* causes an NMI if Port 061h bit 3 is a "0" and NMIs are enabled. Parity errors and uncorrectable system errors exemplify problems that might cause an expansion board to assert IOCHK*.

4.0 EISA Connector Pinout

The following table lists the pinout of the EISA connector. Rows A, B, C, and D form the ISA compatible portion of the connector. Rows E, F, G, and H include the new pins added for EISA unique applications.

ROW F ROW B ROW E ROW A
1 GND 1 GND 1 CMD* 1 IOCHK*
2 +5V 2 RESDRV 2 START* 2 D<7>
3 +5V 3 +5V 3 EXRDY 3 D<6>
4 RESERVED4 IRQ<9> 4 EXEW* 4 D<5>
5 RESERVED5 -5V 5 GND 5 D<4>
ACCESS KEY 6 DRQ<2> ACCESS KEY 6 D<3>
7 RESERVED7 -12V 7 EX16* 7 D<2>
8 RESERVED8 NOWS* 8 SLBURST*8 D<1>
9 +12V 9 +12V 9 MSBURST*9 D<0>
10 M-IO 10 GND 10 W-R 10 CHRDY
11 LOCK* 11 SMWTC* 11 GND 11 AENx
12 RESERVED12 SMRDC* 12 RESERVED12 SA<19>
13 GND 13 IOWC* 13 RESERVED13 SA<18>
14 RESERVED14 IORC* 14 RESERVED14 SA<17>
15 BE*<3> 15 DAK*<3> 15 GND 15 SA<16>
ACCESS KEY 16 DRQ<3> ACCESS KEY 16 SA<15>
17 BE*<2> 17 DAK*<1> 17 BE*<1> 17 SA<14>
18 BE*<0> 18 DRQ<1> 18 LA*<31> 18 SA<13>
19 GND 19 REFRESH*19 GND 19 SA<12>
20 +5V 20 BCLK 20 LA*<30> 20 SA<11>
21 LA*<29> 21 IRQ<7> 21 LA*<28> 21 SA<10>
22 GND 22 IRQ<6> 22 LA*<27> 22 SA<9>
23 LA*<26> 23 IRQ<5> 23 LA*<25> 23 SA<8>
24 LA*<24> 24 IRQ<4> 24 GND 24 SA<7>
ACCESS KEY 25 IRQ<3> ACCESS KEY 25 SA<6>
26 LA<16> 26 DAK*<2> 26 LA<15> 26 SA<5>
27 LA<14> 27 T-C 27 LA<13> 27 SA<4>
28 +5V 28 BALE 28 LA<12> 28 SA<3>
29 +5V 29 +5V 29 LA<11> 29 SA<2>
30 GND 30 OSC 30 GND 30 SA<1>
31 LA<10> 31 GND 31 LA<9> 31 SA<0>
ROW H ROW D ROW G ROW C
1 LA<8> 1 M16* 1 LA<7> 1 SBHE*
2 LA<6> 2 IO16* 2 GND 2 LA<23>
3 LA<5> 3 IRQ<10> 3 LA<4> 3 LA<22>
4 +5V 4 IRQ<11> 4 LA<3> 4 LA<21>
5 LA<2> 5 IRQ<12> 5 GND 5 LA<20>
ACCESS KEY6 IRQ<15> ACCESS KEY6 LA<19>
7 D<16> 7 IRQ<14> 7 D<17> 7 LA<18>
8 D<18> 8 DAK*<0> 8 D<19> 8 LA<17>
9 GND 9 DRQ<0> 9 D<20> 9 MRDC*
10 D<21> 10 DAK*<5> 10 D<22> 10 MWTC*
11 D<23> 11 DRQ<5> 11 GND 11 D<8>
12 D<24> 12 DAK*<6> 12 D<25> 12 D<9>
13 GND 13 DRQ<6> 13 D<26> 13 D<10>
14 D<27> 14 DAK*<7> 14 D<28> 14 D<11>
ACCESS KEY15 DRQ<7> ACCESS KEY15 D<12>
16 D<29> 16 +5V 16 GND 16 D<13>
17 +5V 17 MASTER16*17 D<30> 17 D<14>
18 +5V 18 GND 18 D<31> 18 D<15>
19 MAKx*   19 MREQx*  

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